It would appear that AMD is working on something very interesting. According to sources familiar with the matter they are actively working on a 15 tile design for AMD Milan. Considering 1 of these tiles need to be an IO die, this implies that there will be at least one Milan variant with 14 dies/tiles compared to Rome's 8. Now all of these cannot be CPU tiles due to hardware limitations, according to an engineer I talked to and this is where things get exciting I might add, so some of these 14 tiles are bound to be HBM memory.
AMD's powerful Milan CPU variant will have 15 tiles compared to Rome's 9
Now here's the thing, 8 channel DDR4 only has enough bandwidth available to optimally handle 10 CPU dies (80 CPU cores) at max. This means that you are looking at either an 8-die design (64 CPU cores) or a 10-die design as far as the CPU side goes. Leaving the IO die aside, this leaves 6 or 4 tiles unaccounted for and these are probably going to end up as HBM. HBM can offer substantial speedup but this implies that this particular variant is going to be using an interposer. Long story short, this means, unless AMD chooses to delay this variant till DDR5, you are looking at either an 8+6+1 configuration (CPU + HBM + IO) or a 10+4+1 configuration (CPU + HBM + IO).
An interposer based design with HBM onboard would be able to offer much faster access and transfer times than traditional DDR-based memory where the DDR channel can act as a bottleneck. With the interconnect, IO and interposer the only bottleneck between the CPU cores and HBM memory (pardon the redundancy), this is going to result in some significant speedups for applications that rely heavily on memory - considering this setup is going to result in a faster memory standard than the one we have currently (RAM).
It is worth mentioning that previous leaks have pointed out to AMD Milan having an 8+1 design. Depending on how you interpret that, it could mean that Milan actually has two variants: an exotic one and a normal compute focused one. It is also worth pointing out that the primary reason we think AMD is going with an HBM integrated design is because of the limitations of DDR4, something DDR5 could potentially resolve. There's not much else to add here, so this is going to be a rather short post.
