Intel held its Architecture Day 2020 for the press on August 11 and revealed quite a few technological innovations but the star of the show for architecture fans was the company's SuperFin process enhancement. Intel joked about their ++++ improvements on 14nm and revealed a new FinFET type for 10nm called SuperFin which allowed them to gain several plusses worth of improvement in one go. According to Intel and the benchmarks they provided, the improvement in performance is roughly equal to one node shrink.
Intel's 10nm SuperFin transistor achieves ~17.5% performance uplift and significantly higher clock speeds compared to vanilla 10nm
Intel's 10nm has gained quite a reputation for being broken but it looks like the company has not only managed to fix problems with the original 10nm process but improve it to get several iterations worth of performance uplift in a single go. A single "+" iteration previously gave a performance uplift of around 5% but with 10nm SuperFin enhanced, the intranode performance uplift is roughly 17.5% when compared to vanilla 10nm.
Before we go any further, here is an introduction to Intel's 10nm SuperFin from Ruth Brian herself:
We are redefining [the FinFET] to deliver an unprecedented level of performance uplift. We achieve this through a combination of innovations across the entire process stack from the bottom of the transistor channel all the way to the top interconnect metal layers. Within the transistor, we improved epitaxial growth of crystal structures on the source and drain, increasing the strain and reducing resistance. It allowed more current to flow through the channel.
We had an enhanced source drain architecture driving additional higher channel mobility and enabling charge carriers to move more quickly. Additionally, we had a gate pitch that we've included to provide higher drive currents for certain chip functions that require the utmost performance. Moving up to the metal stack a new thin barrier reduces via resistance by up to 30% enhancing interconnect performance.
The final Innovation is a new super MIM metal insulator metal capacitor when compared to the industry standard, it delivers a 5x increase in capacitance within the same footprint driving a voltage reduction that translates to dramatically improved product performance. This is an industry first technology that far exceeds the current capabilities of other manufacturers. This Innovation is enabled by a new class of high-k dielectric materials stacking ultra thin layers just several angstroms thick to form a repeating super lattice structure.
The combined power of these innovations enable us to deliver a dramatic process performance boost that makes it the largest single node enhancement in Intel history. In one single internode enhancement we delivered essentially the same level of performance achieved over multiple steps at 14 nanometer and nearly the equivalent performance of a full node transition. This process boost will take Intel products to a new level in 2020 and beyond. – Ruth Brian, Intel Fellow, Architecture Day 2020.
Here are some interesting tidbits about Intel's SuperFin transistor:
Intel's SuperFin transistor was first developed when trying to fix 10nm and was initially named 10nm+. Intel realized however, that since previous "+" iterations had only achieved 1/3 of the performance uplift, this was better served with its own proper name.
Intel's Tiger Lake processors are based on SuperFin technology and are able to achieve astonishingly high clock rates for a 10nm chip. You can read more about that in our deep dive by clicking the link.
Intel's Ice Lake processors are based on vanilla 10nm and not SuperFin.
The company is already working on SuperFin enhanced but has not named that yet.
To prove its point, Intel showed benchmarks with all the "+" iterations of 14nm detailed. Each plus got roughly around a 5% improvement compared to the previous node. Intel's 10nm SuperFin on the other hand achieves more than three times that amount in one go. And that's not all! Intel is already working on a SuperFin Enhanced transistor that they have yet to name properly.
Here is Intel's Ruth Brian on the subject of SuperFin Enhanced:
Our friends in the Datacenter saw what we were developing with the new Super Fin technology with the client group. They asked us to make some further enhancements for data center products specifically. Servers benefit from interconnect enhancements to the large amount of data that needs to be shared across the chip. So in addition to continue transistor optimization to deliver more internode performance, we also focused on improving the metal staff with interconnect layer optimizations that make data center scale fabrics for CPU and GPU more easily routable. We’ll have a lot more to say about this enhanced technology in the near future. – Ruth Brian, Intel Fellow, Architecture Day 2020.
