Intel has powered on the Ponte Vecchio A0 silicon and it seems to be working perfectly. This is great news for Intel investors because Ponte Vecchio was the company's most ambitious moonshot in quite a while and considering it had no prior discrete graphics experience it is very impressive that Masooma Bhaiwala and her team, led by Raja Koduri seem to have gotten it right from the get-go.
Intel also admitted several faults in its graphics side during Intel Architecture Day 2021 but also said that they had fixed every last one of those with the Xe HPC architecture. The graph below shows a blue line (Intel graphics) and a green line (a competitor that is likely NVIDIA). As you can see, before 2021, the blue line was significantly under the green line but as of the Ponte Vecchio A0 silicon power on, this has changed.
Intel revealed that building Ponte Vecchio had required a recreation and retooling of basically *everything* involved in the design process.
The Ponte Vecchio package consists of 47 tiles that are built on different foundries (some in Intel, some in TSMC) and require a ton of packaging technologies to come together as a cohesive whole.
The team at Folsom is measuring 45 TFLOPs of FP32 throughput, 5 TBps of memory fabric bandwidth and 2 TBps of connectivity bandwidth validating that all parts of the A0 silicon are working correctly and track to be a major breakthrough in graphics.
No demo is ever complete without benchmarks and Intel even threw in some Resnet benchmarks that show that Intel has broken through the world record score with the A0 Ponte Vecchio silicon:
Intel's Xe HPC will exist in 1 stack and 2 stack designs and Xe Link will be used to couple Ponte Vecchio's in multiple subsystems.
Unlike Xe HPG, an Xe HPC core in the Ponte Vecchio GPU has 8 vector engines (512 bit) and 8 matrix engines (4096 bit).
It is clear that Intel appears to have overcome the valley of stagnation and is making significant progress in leaps and bounds when it comes to high performance graphics. The Aurora super computer will utilize Ponte Vecchio GPUs and the company showed off a single Aurora Blade which will constitute one computational unit of the supercomputing cluster.
The rest of the Xe HPC and Ponte Vecchio presentation is given below:
