Intel Max Series Data Center GPU: 128GB HBM2e, 52 TFLOPs Per OAM, 8 OAM Max, Up To 2x Faster Than NVIDIA A100 In Specific Workloads

Usman Pirzada

Intel, today, announced the Intel Data Center GPU - which is the same platform we know and love as Ponte Vecchio and the idea that kickstarted Intel's GPU ambitions. Intel has shared a lot of information and benchmarks on this platform and considering it has already started shipping to Argonne, its not really surprising that we are starting to see actual performance comparisons now.

Intel formally launches Ponte Vecchio as Data Center GPU Max, server blades already shipping

Related Story Intel Granite Rapids “Up To 128 P-Core” & Sierra Forest “Up To 288 E-Core” CPU Specs Leak, Massive LGA 7592 & LGA 4710 Motherboards Pictured Too

The Intel 'Ponte Vecchio' GPU or the 'Intel Data Center GPU Max Series' as the company now likes to call it, is a major product which has 128 Xe Cores, 128 RT cores (making it the only HPC / AI GPU that has a native raytracing core), up to 64 MB of L1 Cache and up to 408 MB of L2 cache. 128GB of HBM2e has also been used and the IO will connect up to 8 discrete dies. PCIe Gen 5 is being used along with Xe Link to deliver a tremendous amount of processing power. It is created using a mix of Intel 7, TSMC N5 and TSMC N7 packaged through EMIB and Foveros approaches.

intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-054
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-053

Max Series GPUs will be available in several form factors to address different customer needs:

  • Max Series 1100 GPU: A 300-watt double-wide PCIe card with 56 Xe cores and 48GB of HBM2e
    memory. Multiple cards can be connected via Intel Xe Link bridges.
  • Max Series 1350 GPU: A 450-watt OAM module with 112 Xe cores and 96GB of HBM.
  • Max Series 1550 GPU: Intel’s maximum performance 600-watt OAM module with 128 Xe
    cores and 128GB of HBM.

Intel is saying the architecture will allow up to 8 OAMs to be connected for absolute beast mode performance and based on the numbers they gave for 4 OAMs we can calculate the following:

  • 1 OAM: 128GB HBM2e, 128 Xe Cores, 600W TDP, 52TFLOPs, 3.2 TBs/ memory bandwidth
  • 2 OAM: 256GB HBM2e, 256 Xe Cores, 1200W TDP, 104 TFLOPS, 6.4 TB/s memory bandwidth
  • 4 OAM: 512GB HBM2e, 512 Xe Cores, 2400W TDP, 208 TFLOPS, 12.8 TB/s memory bandwidth

Now let's talk about performance.

Max Series GPUs deliver up to 128 Xe-HPC cores, the new foundational architecture targeted at the most demanding computing workloads. Additionally, the Max Series GPU features:

Intel is claiming that each OAM is 2x fater than an NVIDIA 100 in OpenMC and miniBUDE.

Intel states the Intel Data Center GPU Max Series has an aggregate 1.5x performance lead in ExaSMR - NekRS virtual nuclear reactor simulation workloads like AdvSub, FDM (FP32), AxHelm (FP32) and AxHelm (FP64).

Finally, they are also claiming the performance crown (when compared with the NVIDIA A100) on financial workloads like Riskfuel which are used to train credit options pricing models.

Intel also reiterated its intention to release the beastly successor to Ponte Vecchio, which will be Rialto Bridge. It will house up to 160 Xe cores in a new OAM v2 form factor. The biggest change to the GPU is in the die layout. While Ponte Vecchio has 16 Xe-HPC dies, each with 8 Xe cores for a total of 128 cores or 16,384 ALUs, the Rialto Bridge GPU comes with 8 16 Xe-HPC dies. So that should be 20 Xe cores per die for a total of 160 Xe cores on the 8 dies. That rounds up to 20,480 ALUs which is a 25 percent increase over its predecessor.

 

The full presentation can be seen below:

intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-002
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-071
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-070
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-069
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-068
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-067
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-066
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-065
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-064
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-063
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-062
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-061
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-060
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-059
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-058
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-057
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-056
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-055
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-054
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-053
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-052
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-051
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-050
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-049
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-048
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-047
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-046
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-045
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-044
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-043
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-042
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-041
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-040
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-039
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-038
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-037
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-036
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-035
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-034
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-033
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-032
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-031
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-030
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-029
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-028
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-027
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-026
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-025
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-024
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-023
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-022
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-021
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-020
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-019
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-018
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-017
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-016
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-015
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-014
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-013
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-012
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-011
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-010
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-009
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-008
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-007
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-006
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-005
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-004
intel-sc-22-press-deck-final-embargo-6am-pt-nov-9-1-page-003
Share this story

Comments