In less than 24 hours, AMD will be unveiling its next-gen EPYC CPU family codenamed Genoa that utilizes the brand new Zen 4 core architecture.
AMD Is Unveiling Its Next-Gen EPYC Genoa "Zen 4" Data Center CPU Family Today, Tune In & Watch The Livestream Here!
The AMD Zen 4 lineup will be split into three families, the standard Zen 4 for EPYC Genoa, the Compute Density-Optimized Zen 4C for EPYC Bergamo, and the Cache-Optimized Zen 4 V-Cache within the EPYC Genoa-X series. Furthermore, the lineup will be featuring a cost-optimized and entry-level server offering known as EPYC Siena which will feature the same Zen 4 cores but on an entirely new platform known as SP6 which will once again focus on optimizing TCO compared to SP5. The lineup will be branded under the EPYC 8004 family. We covered the initial specs for the Zen 4 server family here already.
Join us Nov. 10 at 10am Pacific for “together we advance_data centers”, a livestream premiere to unveil the next generation of AMD server processors.
🔵Tune in to the AMD YouTube channel and sign up for an email reminder. #AMD #TogetherWeAdvance #datacenters
— AMD (@AMD) November 1, 2022
AMD EPYC Genoa "Zen 4" Server CPU Lineup
The standard Zen 4 lineup will feature up to 12 CCDs, 96 cores, and 192 threads. Each CCD will come with 32 MB of L3 cache and 1 MB of L2 cache per core. The EPYC 9004 CPUs will pack the latest instructions such as BFLOAT16, VNNU, AVX-512 (256b data path), addressable memory of 57b/52b, and an updated IOD with an internal AMD Gen3 Infinity Fabric architecture with higher bandwidth (die-to-die interconnect).
The platform will feature support for 12 DDR5 channels with up to 4800 Mbps DIMM support and include options for 2,4,6,8,10,12 interleaving. Both RDIMM & 3DS RDIMM will be supported with 2 DIMMs per channel for up to 6 TB/ capacities per socket (using 256 GB 3DS RDIMMs). There will be 160 gen 5 lanes available on the 2P platform, 12 PCIe Gen 3 lanes (8 lanes on 1P), 32 SATA lanes, & 64 IO lanes supporting CXL 1.1+ with bifurcations down to x4 and SDCI (Smart Data Cache Injection).
'AMD's EPYC 9000 "Genoa" CPU lineup for servers is going to offer a huge uplift in performance. We have already seen a partial 128-core / 256-thread configuration defeating all of the current-gen server chips so a 192-core and 384-thread dual-socket configuration is going to shatter some world records for sure. The AMD EPYC 9000 Genoa CPU lineup is expected to enter servers by the end of this year and this will be far ahead of Intel's Sapphire Rapids-SP Xeon lineup which is pushed back into early 2023.
