Intel has revealed some more details about its upcoming Knight’s Landing platform (codenamed KNL) at the Supercomputing Conference ’15. Although most of the details surrounding the chips are already out in the open Intel regularly gives out official details confirming the same. This time, not only did they confirm many such details but actually showed the wafer of the Xeon Phi coprocessor. The folks from Anandtech were able to get their hands on some engineering samples as well, a few pictures of which are given below.
A picture of the Knight's Landing Wafer. Image Credits: Anandtech
Intel shows off Knight's Landing wafer at SC15 - huge die size at the 14nm node
According to Anandtech’s Ian Cutress, the die size of the new Knight’s Landing chips will be around ~683mm^2 – which as any enthusiast knows is absolutely huge (and that on a 14nm node!). It will ofcourse come in two form factors unlike Knight’s Corner which only came in one: the old form ‘PCI-E card’ form factor and the new socket form factor. It is worth nothing that the PCI-E form factor was a co-processor which required an internal OS whereas the socket form factor will not have any such requirements and will act as a normal processor. KNL has a total of 36 PCIe lanes which can host 2 Knight’s Corner co-processor cards as well.
Knight’s Landing uses modified silvermont cores (x86 ofcourse). It is also one of the first mass produced components developed for this market segment that features stacked DRAM (short of AMD’s Fury lineup, which doesn’t really count here). Since the GPU form factor is usually limited (to heck) by the PCI-E lane, an alternative CPU form factor is also provided which gives super-low latency and almost no bottlenecks. There are connections for additional DDR4 2400Mhz memory. Keep in mind that we are talking about a socket-able, packaged processor here, not just a GPU sized product.
The HMC will not actually be placed or stacked upon the die. Using the 2.5 D stacking that should now be pretty familiar for our readers, Intel will actually be surrounding the Xeon Phi die using a Micron-Intel custom made, super-high bandwidth, parallel path interface that will make the HMC appear as if its on the die. Infact it will act more or less like an L3 cache worth 16GB. The Hybrid Memory Cube used in the Knights Landing Xeon Phi package will feature upto 2000 TSVs and an ASIC at the base of the HMC to manage the DRAM package.
Intel also confirmed the following details (pardon the redundancy): There will be two form factors, namely a bootable host processor and a PCIe coprocessor. Upto 384GB of DDR4 RAM using 6 Channels with 90GB/s of sustained bandwidth. The server density will be 3+ KNL in 1U configuration. Upto 16GB of MCDRAm will be supported at launch which is 5x more energy efficient than GDDR5 and 3x denser than GDDR5. It will have NUMA support and is developed in partnership with Micron Technology.
The KNL platform will have over 8 Billion transistors and is based entirely on Intel’s 14nm process. It will have upto 72 cores distributed on 36 tiles. Each core can support 4 threads which brings the total thread count upto 288 concurrent threads. Each “tile” will have 2 cores with 2 vector processor units per core.
KNL will support a peak DP performance of 3+ TFLOPS and over 6 TFLOPs in SP. It will also have three times the single threaded performance of Knight’s Corner which is quite a huge upgrade. Memory bandwidth will be over 400 GB/s. Knight's Landing will get first availability in 2H’15. The platform that will succeed Knight’s Landing is Knight’s Hill and will be based on the 10nm process and have an integrated 2nd Generation Omni-Path Host Fabric interface (KNL has the 1st Generation Omni-Path interface).
